Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines

ABSTRACT

A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacers, and within the respective recesses; and f) providing a capacitor dielectric layer and a second capacitor plate layer over the first capacitor plate layer. In another aspect, a semiconductor processing method of processing relative to a conductive line includes, i) providing a pair of sidewall spacers laterally outward of an electrically conductive line; and ii) etching material over the conductive line between the sidewall spacers selectively relative to the sidewall spacers to form a recess over the conductive line relative to the sidewall spacers. Capacitor and conductive line constructions produced according to the above and other methods are also disclosed.

TECHNICAL FIELD

[0001] This invention relates to capacitor formation in semiconductorwafer processing, and to resultant capacitor constructions. Theinvention secondarily relates to conductive line formation insemiconductor wafer processing, and to resultant conductive lineconstructions.

BACKGROUND OF THE INVENTION

[0002] As DRAMs increase in memory cell density, there is a continuingchallenge to maintain sufficiently high storage capacitance despitedecreasing cell area. Additionally, there is a continuing goal tofurther decrease cell area.

[0003] The principal way of increasing cell capacitance is through cellstructure techniques. Such techniques include three-dimensional cellcapacitors, such as trenched or stacked capacitors. This inventionconcerns stacked capacitor cell constructions, including what arecommonly known as crown or cylindrical container stacked capacitors.Aspects of the invention are also applicable to conductive linefabrication and resultant construction.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0005]FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with the invention.

[0006]FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1.

[0007]FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 2.

[0008]FIG. 4 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 3.

[0009]FIG. 5 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0010]FIG. 6 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0011]FIG. 7 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 6.

[0012]FIG. 8 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 7.

[0013]FIG. 9 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

[0014]FIG. 10 is a view of the FIG. 1 wafer fragment at a processingstep subsequent to that shown by FIG. 9.

[0015]FIG. 11 is an alternate embodiment view of the FIG. 1 waferfragment at an alternate embodiment processing step subsequent to thatshown by FIG. 4.

[0016]FIG. 12 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that shown by FIG. 11.

[0017]FIG. 13 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that shown by FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0019] In accordance with one aspect of the invention, a semiconductorprocessing method of forming a capacitor construction comprises thefollowing steps:

[0020] providing a pair of electrically conductive lines havingrespective electrically insulated outermost surfaces;

[0021] providing a pair of sidewall spacers laterally outward of each ofthe pair of conductive lines;

[0022] etching material over the pair of conductive lines between therespective pairs of sidewall spacers selectively relative to thesidewall spacers to form respective recesses over the pair of conductivelines relative to the sidewall spacers, the etching leaving theoutermost conductive line surfaces electrically insulated;

[0023] providing a node to which electrical connection to a capacitor isto be made between the pair of conductive lines, one sidewall spacer ofeach pair of sidewall spacers being closer to the node than the othersidewall spacer of each pair;

[0024] providing an electrically conductive first capacitor plate layerover the node, the one sidewall spacers, and within the respectiverecesses; and

[0025] providing a capacitor dielectric layer and a second capacitorplate layer over the first capacitor plate layer.

[0026] In accordance with another aspect of the invention, asemiconductor processing method of processing relative to a conductiveline comprises the following steps:

[0027] providing a pair of sidewall spacers laterally outward of anelectrically conductive line; and

[0028] etching material over the conductive line between the sidewallspacers selectively relative to the sidewall spacers to form a recessover the conductive line relative to the sidewall spacers.

[0029] Capacitor and conductive line constructions produced according tothe above and other methods are also disclosed.

[0030] A semiconductor processing method of forming a capacitorconstruction is first described with reference to FIG. 1 where asemiconductor wafer in process is indicated generally with referencenumeral 10. Such comprises a bulk monocrystalline silicon substrate 12and electrically isolating field oxide regions 14. Active area 16 liestherebetween. A stack of layers is shown for formation of a plurality ofelectrically conductive gate lines for fabrication of DRAM circuitry.Specifically, a layer 18 comprises a gate oxide layer, and a layer 20comprises conductively doped polysilicon, a layer 22 comprises a higherconductivity silicide, such as WSi_(x). Example thicknesses for layers18, 20 and 22 are 90 Angstroms, 1500 Angstroms, and 1200 Angstroms,respectively. First and second capping layers 24 and 26, respectively,are provided outwardly of silicide layer 22. Purposes thereof will beapparent subsequently. A preferred material for layer 24 is Si₃Ni₄,while a preferred material for layer 26 is undoped SiO₂. Examplepreferred thicknesses for layers 24 and 26 are 2000 Angstroms each.Although not shown, a thin layer of oxide (i.e., 350 Angstroms) wouldpreferably also be provided between layers 22 and 24.

[0031] Referring to FIG. 2, the composite layers are collectivelypatterned to form the illustrated conductive line stacks 27, 28, 29 and30. Such comprise respective conductive portions 31, 32, 33 and 34, withthe remaining respective portions thereof in the preferred embodimentconstituting electrically insulative material. The discussion proceedswith reference to electrically conductive line pairs 31 and 32. In thepreferred embodiment, identical processing also occurs relative toconductive line pair 33 and 34, as will be apparent. Electricallyconductive lines 31 and 32 have respective outermost surfaces 35 and 36which are effectively insulated by first capping layer 24. The patternedcapping layer 24 forms respective first electrically insulative caps 37and 38 over outer surfaces 35 and 36, effectively providing electricalinsulation thereof. Patterned second capping layer 26 defines respectivesecond caps 39 and 40 over first caps 37 and 38, respectively. Secondcaps 39 and 40 are preferably chosen to comprise a material which isselectively etchable relative to that of first caps 37 and 38.

[0032] Referring to FIG. 3, an electrically insulative spacer layer 42is deposited. An example and preferred material is Si₃N₄ deposited to anexample thickness of 700 Angstroms.

[0033] Referring to FIG. 4, the spacer layer 42 is anisotropicallyetched to provide a pair of sidewall spacers 43, 44 laterally outward ofconductive line 31, first cap 37 and second cap 39, and also a pair ofsidewall spacers 45 and 46 laterally outward of conductive line 32,first cap 38 and second cap 40. The material of second caps 39 and 40 isadvantageously chosen to be selectively etchable relative to sidewallspacers 43, 44, 45 and 46. Most preferred, first caps 37 and 38 arechosen to constitute the same predominant Si₃N₄ material as spacers 43,44, 45 and 46.

[0034] Diffusion regions 52, 54 and 56 are at some point providedrelative to bulk substrate 12, as shown. Region 54 comprises a sharedbit contact node for a bit line in accordance with fabrication of a DRAMarray, whereas diffusion regions 52 and 56 constitute respective nodesto which electrical connection to a capacitor is to be made. Thus withrespect to the above continuing discussion, diffusion region 52constitutes a capacitor connection node provided between pair ofconductive lines 31 and 32. The sidewall spacers 44 and 45 of each ofthe two described pairs of sidewall spacers are closer to node 52 thanthe other sidewall spacers 43 and 46 of each respective pair.

[0035] Referring to FIG. 5, second caps 39 and 40 are etched between therespective pairs of sidewall spacers 43, 44 and 45, 46, and selectivelyrelative to first caps 37 and 38 to form recesses 48 and 50 over thepair of conductive lines 31 and 32, respectively, relative to sidewallspacers 43, 44 and 45, 46, respectively. Thus, material is etched overthe pair of conductive lines between the respective spacers, which inthe preferred embodiment comprises an electrically insulative materialof SiO₂. Further, outermost conductive line surfaces 35 and 36 remainelectrically insulated by material 24 after the etching step.

[0036] Referring to FIG. 6, an electrically insulating layer 60 isdeposited and planarized outwardly relative to conductive lines 31 and32, and within recesses 48 and 50. An example and preferred material forlayer 60 is borophosphosilicate glass (BPSG).

[0037] Referring to FIG. 7, insulating layer 60 is patterned and etchedto define a capacitor container opening 62 therethrough relative to node52. Capacitor opening 62 is patterned to have a pair of outer lateralsidewalls 63 and 64. Lateral sidewall 63 is positioned or receivedwithin the lateral confines of sidewall spacers 45 and 46, while lateralsidewall 64 is positioned or received within the lateral confines ofsidewall spacers 43 and 44.

[0038] Referring to FIG. 8, an electrically conductive capacitor platelayer 65 is deposited over electrically insulating layer 60 and withincapacitor opening 62, and accordingly over node 52, at least the onesidewall spacers 44 and 45 and within respective recesses 48 and 50. Apreferred composition for layer 65 is conductively doped polysilicon.

[0039] Referring to FIG. 9, layer 65 is preferably chemical-mechanicalpolished (CMPed) to effectively define a first capacitor plate 66effectively in the shape of a container. The recessing or etching ofmaterial between the illustrated sidewall spacers effectively results inlayer 65 serpentining thereover, thus increasing surface area over thatwhich would otherwise occur were such recesses not provided. Further inaccordance with the preferred process, container 66 effectively includessidewalls 68 and 70 which effectively project outwardly relative toconductive lines 31 and 32 within the lateral confines of respectiverecesses 48 and 50 between pairs of sidewall spacers 43, 44 and 45, 46,respectively.

[0040] Referring to FIG. 10, a capacitor dielectric layer 75 and asecond capacitor plate layer 80 are provided over patterned firstcapacitor plate 65/66. A preferred material for layer 75 is an oxide, anONO composite or a ferroelectric material. Layer 80 preferablyconstitutes conductively doped polysilicon. Processing would typicallyproceed in the fabrication of a DRAM array by patterning and isolating acontact opening through layers 80 and 75 over and to node 54. Theopening would then be preferably separately plugged with tungsten.Subsequently, an electrically conductive layer would be deposited andpatterned for fabrication of a bit line which ohmically connects withthe plug.

[0041] Although the invention primarily spawned from concerns associatedwith maximizing capacitance in a capacitor construction, the artisanwill appreciate applicability of the invention relative to fabricationof and resultant electrically conductive lines apart from capacitorfabrication.

[0042] The above described embodiment etched capping layer 26/caps 39,40 without any masking of such capping material between the respectivepairs of sidewall spacers. An alternate and preferred embodiment wherebysome of said material between the respective pairs of sidewall spacersis masked during etching is described during with reference to FIGS.11-13. Like numerals from the first described embodiment are utilizedwhere appropriate, with differences being indicated by the suffix “b” orwith different numerals.

[0043]FIG. 11 illustrates a wafer fragment 10 b shown at a processingstep subsequent to that depicted by FIG. 4 of the first describedembodiment. Here, second capping layer 26/caps 39, 40 are not etchedselectively relative to the sidewall spacers prior to provision ofplanarized electrically insulating layer 60 b.

[0044] Referring to FIG. 12, the mask and etching utilized to producecapacitor container opening 62 also comprises etching of material 26 toproduce recesses 48 b and 50 b in the same essential step utilized toproduce the capacitor container opening. Thus in the first describedembodiment, recesses 48 and 50 extend completely across the respectiveconductive lines between the respective sidewall spacers. In the FIGS.11-13 embodiment, recesses 48 b and 50 b extend only partially acrossthe respective lines between the respective sidewall spacers.

[0045]FIG. 13 illustrates resultant patterning to produce the sameessential construction as the first described embodiment, but forremaining second caps 39 b and 40 b spanning only a portion of the linewidth, and thus providing a gap between the respective inner sidewallspacers and the respective cap 39 b or 40 b.

[0046] This second described embodiment is preferred over the firstdescribed embodiment in leaving gate oxide over the substrate area, suchas the area over diffusion region 54, until such time as the substratearea is exposed for electrical contact therewith.

[0047] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming a capacitor constructioncomprising the following steps: providing a pair of electricallyconductive lines having respective electrically insulated outermostsurfaces; providing a pair of sidewall spacers laterally outward of eachof the pair of conductive lines; etching material over the pair ofconductive lines between the respective pairs of sidewall spacersselectively relative to the sidewall spacers to form respective recessesover the pair of conductive lines relative to the sidewall spacers, theetching leaving the outermost conductive line surfaces electricallyinsulated; providing a node to which electrical connection to acapacitor is to be made between the pair of conductive lines, onesidewall spacer of each pair of sidewall spacers being closer to thenode than the other sidewall spacer of each pair; providing anelectrically conductive first capacitor plate layer over the node, theone sidewall spacers, and within the respective recesses; and providinga capacitor dielectric layer and a second capacitor plate layer over thefirst capacitor plate layer.
 2. The semiconductor processing method ofclaim 1 wherein the etching is conducted without masking any of saidmaterial between the respective pairs of sidewall spacers.
 3. Thesemiconductor processing method of claim 1 wherein the etching isconducted with some of said material between the respective pairs ofsidewall spacers being masked.
 4. The semiconductor processing method ofclaim 1 wherein the material etched over the pair of conductive linesbetween the respective pair of spacers comprises electrically insulativematerial.
 5. The semiconductor processing method of claim 1 wherein thestep of providing the first capacitor plate layer comprises: after theetching step, providing an electrically insulating layer outwardly ofthe conductive lines and within the recesses; patterning and etching theinsulating layer to define a capacitor container opening therethroughover the node; and depositing the electrically conductive capacitorplate layer over the electrically insulating layer and within thecapacitor opening.
 6. The semiconductor processing method of claim 5wherein the capacitor opening is patterned to have a pair of outerlateral sidewalls, each lateral sidewall of the pair being positionedbetween a respective one of the pairs of sidewall spacers.
 7. Thesemiconductor processing method of claim 5 wherein the material etchedover the pair of conductive lines between the respective pair of spacerscomprises electrically insulative material.
 8. The semiconductorprocessing method of claim 1 wherein the step of providing the firstcapacitor plate layer comprises: providing an electrically insulatinglayer outwardly of the conductive lines; patterning and etching theinsulating layer to define a capacitor container opening therethroughover the node, the capacitor opening being patterned to have a pair ofouter lateral sidewalls, each lateral sidewall of the pair beingpositioned between a respective one of the pairs of sidewall spacers,the etching of said material to form the recesses and the etching of theinsulating layer being conducted in the same etching step; anddepositing the electrically conductive capacitor plate layer over theelectrically insulating layer and within the capacitor opening.
 9. Asemiconductor processing method of forming a capacitor constructioncomprising the following steps; providing a pair of electricallyconductive lines having respective first electrically insulative capsthereover, and respective second caps over the first caps, the secondcaps being selectively etchable relative to the first caps; providing apair of sidewall spacers laterally outward of each of the pair ofconductive lines and the first and second caps, the second caps beingselectively etchable relative to the sidewall spacers; etching therespective second caps between the respective pairs of sidewall spacersselectively relative to the sidewall spacers and the first caps to formrespective recesses over the pair of conductive lines relative to thesidewall spacers; providing a node to which electrical connection to acapacitor is to be made between the pair of conductive lines, onesidewall spacer of each pair of sidewall spacers being closer to thenode than the other sidewall spacer of each pair; providing anelectrically conductive first capacitor plate layer over the node, theone sidewall spacers, and within the respective recesses; and providinga capacitor dielectric layer and a second capacitor plate layer over thefirst capacitor plate layer.
 10. The semiconductor processing method ofclaim 9 wherein the etching of the second caps is conducted withoutmasking any of the second caps between the respective pairs of sidewallspacers.
 11. The semiconductor processing method of claim 9 wherein theetching of the second caps is conducted with some of the second capsbetween the respective pairs of sidewall spacers being masked.
 12. Thesemiconductor processing method of claim 9 wherein the first caps andsidewall spacers constitute the same material.
 13. The semiconductorprocessing method of claim 9 wherein the first caps and sidewall spacerspredominantly comprise Si₃N₄, and the second caps predominantly comprisesilicon dioxide.
 14. The semiconductor processing method of claim 9wherein the step of providing the first capacitor plate layer comprises:after the etching step, providing an electrically insulating layeroutwardly of the conductive lines and within the recesses; patterningand etching the insulating layer to define a capacitor container openingtherethrough over the node; and depositing the electrically conductivecapacitor plate layer over the electrically insulating layer and withinthe capacitor opening.
 15. The semiconductor processing method of claim14 wherein the capacitor opening is patterned to have a pair of outerlateral sidewalls, each lateral sidewall of the pair being positionedbetween a respective one of the pairs of sidewall spacers.
 16. Thesemiconductor processing method of claim 14 wherein the first caps andsidewall spacers constitute the same material.
 17. The semiconductorprocessing method of claim 14 wherein the first caps and sidewallspacers predominantly comprise Si₃N₄, and the second caps predominantlycomprise silicon dioxide.
 18. The semiconductor processing method ofclaim 14 wherein, the capacitor opening is patterned to have a pair ofouter lateral sidewalls, each lateral sidewall of the pair beingpositioned between a respective one of the pairs of sidewall spacers;and the first caps and sidewall spacers constitute the same material.19. The semiconductor processing method of claim 9 wherein the step ofproviding the first capacitor plate layer comprises: providing anelectrically insulating layer outwardly of the conductive lines;patterning and etching the insulating layer to define a capacitorcontainer opening therethrough over the node, the capacitor openingbeing patterned to have a pair of outer lateral sidewalls, each lateralsidewall of the pair being positioned between a respective one of thepairs of sidewall spacers, the etching of the second caps to form therecesses and the etching of the insulating layer being conducted in thesame etching step; and depositing the electrically conductive capacitorplate layer over the electrically insulating layer and within thecapacitor opening.
 20. A semiconductor processing method of processingrelative to a conductive line comprising the following steps: providinga pair of sidewall spacers laterally outward of an electricallyconductive line; and etching material over the conductive line betweenthe sidewall spacers selectively relative to the sidewall spacers toform a recess over the conductive line relative to the sidewall spacers.21. The semiconductor processing method of claim 20 wherein the etchingis conducted without masking any of said material between the pair ofsidewall spacers.
 22. The semiconductor processing method of claim 20wherein the etching is conducted with some of said material between thepair of sidewall spacers being masked.
 23. The semiconductor processingmethod of claim 20 wherein the electrically conductive line has anoutermost surface, the outermost surface of the electrically conductiveline being electrically insulated, the etching step leaving theoutermost conductive line surface electrically insulated.
 24. Thesemiconductor processing method of claim 20 wherein the conductive lineis provided with a first electrically insulative cap thereover and asecond cap provided over the first cap, the sidewall spacers also beingprovided laterally outward over the first and second caps, the etchingstep comprising etching the second cap selectively relative to the firstcap and sidewall spacers.
 25. The semiconductor processing method ofclaim 24 wherein the first cap and sidewall spacers constitute the samematerial.
 26. The semiconductor processing method of claim 24 whereinthe first cap and sidewall spacers predominantly comprise Si₃N₄, and thesecond cap predominantly comprises silicon dioxide.
 27. A capacitorconstruction comprising: a pair of electrically conductive lines havingrespective electrically insulated outermost surfaces; a pair of sidewallspacers laterally outward of each of the pair of conductive lines;respective recesses over the pair of conductive lines relative to thesidewall spacers; a node between the pair of conductive lines, onesidewall spacer of each pair of sidewall spacers being closer to thenode than the other sidewall spacer of each pair; an electricallyconductive first capacitor plate layer over the node, the one sidewallspacers, and within the respective recesses; and a capacitor dielectriclayer and a second capacitor plate layer over the first capacitor platelayer.
 28. The capacitor construction of claim 27 wherein the recessesextend completely across the respective lines between the respectivesidewall spacers.
 29. The capacitor construction of claim 27 wherein therecesses extend only partially across the respective lines between therespective sidewall spacers.
 30. The capacitor construction of claim 27wherein the first capacitor plate layer is in the shape of a container.31. The capacitor construction of claim 27 wherein the first capacitorplate layer is in the shape of a container, the container havingsidewalls projecting outwardly of the conductive lines within lateralconfines of the respective recesses between the respective pairs ofsidewall spacers.
 32. An electrically conductive line constructioncomprising: an electrically conductive line; an electrically insulativeoutermost cap over the line, the cap having an outermost surface; and apair of sidewall spacers laterally outward of the line and cap, thesidewall spacers projecting outwardly relative to the cap outermostsurface.
 33. The electrically conductive line construction of claim 32wherein the cap and spacers comprise the same predominant material. 34.The electrically conductive line construction of claim 32 wherein thecap and spacers predominantly comprise Si₃N₄.
 35. An electricallyconductive line construction comprising: an electrically conductive linehaving a width; an electrically insulative outermost cap over the line;and a pair of sidewall spacers laterally outward of the line and cap,the cap spanning only a portion of the line width providing a gapbetween one of the pair of spacers and the cap.